Semiconductor memories may control internal circuits thereof by way of signals having various operation timings. Delay circuits may be employed along signal propagation paths in order to establish such various signal operation timings. In particular, high-frequency memories, such as DRAMs, SRAMs, and flash memories, may utilize address transition detection (ATD) circuits to access memory core circuits, such as sense amplifiers and memory cells, in response to address transitions.
FIG. 1 illustrates a conventional general flash memory. The general flash memory may include an address buffer 110, a wordline decoder 120, a bitline decoder 130, a memory cell block 140, an ATD circuit 150, a sense amplifier 160, and an input/output buffer 170. The address buffer 110 is generally capable of transferring external address signals to the wordline and bitline decoders, 120 and 130. A data bit of a memory cell designated by the wordline and bitline decoder 120 and 130 may be driven into the input/output buffer 170 by way of the sense amplifier 160. The sense amplifier 160 is capable of determining a validity of data read out from the selected memory cell. The sense amplifier 160 may also receive signals from the ATD circuit 150, which includes a delay circuit 200. These signals instruct the sense amplifier 160 to exhaust charges on a bitline that may remain after data is sensed. Moreover, the signals from the ATD circuit 150 and the delay circuit 200 may be used to activate the sense amplifier 160.
Generally, operating speeds of integrated circuits are proportional to a power supply voltage (Vdd) level. A higher Vdd often enhances operating speeds, while a lower Vdd often degrades operating speeds. Thus, signals generated from the delay circuit 200 may have different timings as power supply voltage levels vary.
FIG. 2 illustrates the conventional delay circuit 200. The delay circuit 200 may include an inverter 201, a resistor 202, a capacitor 203, an inverter 204, and a NAND gate 205. An input signal at input IN may be applied to one input terminal of the NAND gate 205 through the inverters 201 and 24, and the resistor 202. As is illustrated, the input signal may also be applied to another input terminal of the NAND gate 205.
FIG. 3 illustrates an operational timing diagram of the conventional delay circuit 200 of FIG. 2. As is illustrated, different transition times occur between the input IN node, the intermediate node A, and an output OUT node, in accordance with power supply voltage Vdd variations. The input signal has a longer transition time at Vdd=1.5V than when Vdd=3.5V. Accordingly, the node A, which responds to a rising edge of the input signal passing through the inverter 201, the resistor 202, and the capacitor 203, will reach a low level slower when Vdd=1.5V than when Vdd=3.5V. An output signal generated from the NAND gate 205 responds to a trigger point (T1, T2, or T3) at the node A. As a result, the output signal transitions slower when Vdd=1.5V than when Vdd=3.5V.
Output signal fluctuations from an ATD circuit, along variations of a power supply voltage, may result in memory device malfunctions.